The 60th JSAP Spring Meeting,2013

Presentation information

Regular sessions(Poster presentation)

13. Semiconductors A (Silicon) » 13.6 Silicon devices / Integration technology

[27p-PB5-1~13] 13.6 Silicon devices / Integration technology

Wed. Mar 27, 2013 1:30 PM - 3:30 PM PB5 (2nd gymnasium)

[27p-PB5-6] Threshold Voltage Control Using Second Gate in 4-Terminal Tunnel FinFETs

Wataru Mizubayashi1, 2, Koichi Fukuda1, 2, Takahiro Mori1, 2, Kazuhiko Endo1, 2, Yongxun Liu1, 2, Takashi Matsukawa1, 2, Shininchi O’uch1, 2, Yuki Ishikawa2, Shinji Migita1, 2, Yukinori Morita1, 2, Akihito Tanabe1,2, Junichi Tsukada2, Hiromi Yamauchi2, Meishoku Masahara1,2, Hiroyuki Ota1,2 (GNC-AIST1, NeRI -AIST2)

Keywords:トンネルFET、Vth制御、FinFET