[29a-G2-1~7] 11.5 Junction, circuit fabrication process and digital applications

[29a-G2-2] △Development of the low power shift register memory by LR bias for the SFQ micro processor

^○Ryo Numaguchi¹, Kohei Ehara¹, Akitomo Takahashi¹, Kazuya Hinago¹, Yuki Yamanashi¹, Nobuyuki Yoshikawa¹ (Yokohama National Univ.¹)

Keywords:SFQ、memory、shift register