[29a-G9-1~11] 13.6 Silicon devices / Integration technology

[29a-G9-1] Confirmation of Drain Current Enhancement in Epitaxial-Channel Si TFET with Vertical Tunnel Architecture

^○Yukinori Morita¹, Takahiro Mori¹, Shinji Migita¹, Wataru Mizubayashi¹, Akihito Tanabe¹, Koichi Fukuda¹, Meishoku Masahara¹, Hiroyuki Ota¹ (GNC-AIST¹)

Keywords:TFET、Tunnel FET、トンネルFET