[29p-PB1-1~20] 13.3 Insulator technology

[29p-PB1-20] Suppression of Reaction at Au/Ge Interface by Ultra-thin Insulator Insertion and its Correlation with Fermi Level Pinning

^○Tomonori Nishimura^1,2, Kosuke Nagashio^1,2, Koji Kita^1,2, Akira Toriumi^1,2 (The Univ. of Tokyo¹, JST-CREST²)

Keywords:フェルミレベルピンニング