Statistical Analysis of Minimum Operation Voltage (V<sub>min</sub>) in Fully Depleted Silicon-on-Thin-BOX (SOTB) SRAM Cells

Tomoko Mizutani

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Oral presentation

13. Semiconductors A (Silicon) » 13.4 Devices/Integration Technologies

[18a-A16-1~11] 13.4 Devices/Integration Technologies

Thu. Sep 18, 2014 9:00 AM - 12:00 PM A16 (E307)

9:30 AM - 9:45 AM

[18a-A16-3] Statistical Analysis of Minimum Operation Voltage (V_min) in Fully Depleted Silicon-on-Thin-BOX (SOTB) SRAM Cells

^○Tomoko Mizutani¹, Yoshiki Yamamoto², Hideki Makiyama², Tomohiro Yamashita², Hidekazu Oda², Shiro Kamohara², Nobuyuki Sugii², Toshiro Hiramoto¹ (IIS, Univ. of Tokyo¹, LEAP²)

Keywords:SRAN,最低動作電圧,ばらつき

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Presentation information

[18a-A16-1~11] 13.4 Devices/Integration Technologies

[18a-A16-3] Statistical Analysis of Minimum Operation Voltage (Vmin) in Fully Depleted Silicon-on-Thin-BOX (SOTB) SRAM Cells

[18a-A16-3] Statistical Analysis of Minimum Operation Voltage (V_min) in Fully Depleted Silicon-on-Thin-BOX (SOTB) SRAM Cells