Session information

Oral presentation

13. Semiconductors A (Silicon) » 13.4 Devices/Integration Technologies

[19a-F12-1~13] 13.4 Devices/Integration Technologies

Wed. Mar 19, 2014 9:00 AM - 12:30 PM F12 (F408)

△：Young Scientist Oral Presentation Award Applied
▲：English Presentation
▼：Both Award Applied and English Presentation

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9:00 AM - 9:15 AM

[19a-F12-1] Channel Size Dependence of Low-Frequency Noise in Si Tri-gate Nanowire Transistors

^○Masumi Saitoh¹, Kensuke Ota¹, Chika Tanaka¹, Toshinori Numata¹ (Toshiba Corp.¹)

9:15 AM - 9:30 AM

△ [19a-F12-2] Evaluation of Self-Heating Effects in Nanoscale Bulk and Ultra-Thin BOX SOI MOSFETs Using Four-Terminal Gate Resistance Technique

^○（P）Tsunaki Takahashi¹, Takeo Matsuki³, Takahiro Shinada^2,3, Yasuo Inoue³, Ken Uchida¹ (Dept. Electrical and Electronics Eng., Keio Univ.¹, Nanoelectronics RI, AIST², TIA Headquaters, AIST³)

9:30 AM - 9:45 AM

[19a-F12-3] Analysis of FinFET variability caused by granular work function variation of metal gates

^○Takashi Matsukawa¹, Kouichi Fukuda¹, Yongxun Liu¹, Kazuhiko Endo¹, Junichi Tsukada¹, Hiromi Yamauchi¹, Yuki Ishikawa¹, Shinichi O'uchi¹, Wataru Mizubayashi¹, Hiroyuki Ota¹, Shinji Migita¹, Yukinori Morita¹, Meishoku Masahara¹ (AIST, NeRI¹)

9:45 AM - 10:00 AM

[19a-F12-4] Reduced Minimum Operation Voltage in Fully Depleted Silicon-on-Thin-BOX (SOTB) SRAM Cells

^○Tomoko Mizutani¹, Yoshiki Yamamoto², Hideki Makiyama², Hirofumi Shinohara², Toshiaki Iwamatsu², Hidekazu Oda², Nobuyuki Sugii², Toshiro Hiramoto¹ (IIS, Univ. of Tokyo¹, LEAP²)

10:00 AM - 10:15 AM

[19a-F12-5] Statistical Characteristics Analysis of “N-curve” and Static Noise Margin for Prediction of Yield of SRAM Cell Array

^○Tomoko Mizutani¹, Yoshiki Yamamoto², Hideki Makiyama², Hirofumi Shinohara², Toshiaki Iwamatsu², Hidekazu Oda², Shiro Kamohara², Nobuyuki Sugii², Toshiro Hiramoto¹ (IIS, Univ. of Tokyo¹, LEAP²)

10:15 AM - 10:30 AM

[19a-F12-6] FinFET-based pseudo-spin-MOSFET and its nonvolatile SRAM application

^○Yusuke Shuto^1,2, Shuu'ichirou Yamamoto^1,2, Satoshi Sugahara¹ (ISEL, Tokyo Inst. Tech.¹, KAST²)

Break 10:30〜10:45 (10:30 AM - 10:45 AM)

10:45 AM - 11:00 AM

[19a-F12-7] Self-Image Potential in Electron Transport under Nano-Device Structures

^○（B）Yosuke Tsuchiya¹, Katsuhisa Yoshida¹, Nobuyuki Sano¹ (Inst. Appl. Phys, Univ. of Tsukuba¹)

11:00 AM - 11:15 AM

△ [19a-F12-8] Carrier Mobility and Discrete Impurity Scattering in Nanowire Structures

^○（B）Yuki Tanoue¹, Nobuyuki Sano¹ (Inst. Appl. Phys., Univ. of Tsukuba¹)

11:15 AM - 11:30 AM

△ [19a-F12-9] Impacts of Cross-sectional Shape on Phonon-limited Electron Mobility in Rectangular Ge Nanowires

^○Hajime Tanaka¹, Seigo Mori¹, Naoya Morioka¹, Jun Suda¹, Tsunenobu Kimoto¹ (Kyoto Univ.¹)

11:30 AM - 11:45 AM

[19a-F12-10] On the drain bias dependencies of tunnel FETs

^○Koichi Fukuda¹, Takahiro Mori¹, Wataru Mizubayashi¹, Akito Tanabe¹, Meishoku Masahara¹, Tetsuji Yasuda¹, Shinji Migita¹, Hiroyuki Ota¹, Yukinori Morita¹ (AIST GNC¹)

11:45 AM - 12:00 PM

[19a-F12-11] Performance enhancement of tunnel FinFET by synthetic electric field effect

^○Yukinori Morita¹, Takahiro Mori¹, Shinji Migita¹, Wataru Mizubayashi¹, Akihito Tanabe¹, koichi Fukuda¹, Kazuhiko Endo¹, Takashi Matsukawa¹, Shin-ichi O'uchi¹, Y.X. Liu¹, Meishoku Masahara¹, Hiroyuki Ota¹ (GNC-AIST¹)

12:00 PM - 12:15 PM

[19a-F12-12] Feasibility Study of ON Current Enhancement of TFETs by Utilizing Isovalent Traps

^○Takahiro Mori¹, Yukinori Morita¹, Noriyuki Miyata¹, Shinji Migita¹, Meishoku Masahara¹, Tetsuji Yasuda¹, Hiroyuki Ota¹ (GNC-AIST¹)

12:15 PM - 12:30 PM

[19a-F12-13] Compensation doping effect of TFET using InAs nanowire/Si heterojunction

^○Katsuhiro Tomioka^1,2, Fumiya Ishizaka¹, Eiji Nakai¹, Takashi Fukui¹ (GS-IST and RCIQE¹, JST-PRESTO²)

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