Oral presentation

13. Semiconductors A (Silicon) » 13.3 Si Process・Interconnect・MEMS・Integration

[19p-E14-1~21] 13.3 Si Process・Interconnect・MEMS・Integration

Wed. Mar 19, 2014 1:15 PM - 6:45 PM E14 (E302)

△：Young Scientist Oral Presentation Award Applied
▲：English Presentation
▼：Both Award Applied and English Presentation

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Lunch 11:45〜13:15 (11:45 AM - 1:15 PM)

1:15 PM - 1:30 PM

[19p-E14-1] Process Integration of MOSFETs Fabricated by Full MINIMAL Equipment

^○Fumito Imura¹, Kazuhiro Koga¹, Hitoshi Asano¹, Sommawan Khumpuang^1,2, Shiro Hara^1,2 (MINIMAL¹, AIST²)

1:30 PM - 1:45 PM

[19p-E14-2] Characterization of pn diodes and MOS capacitors fabricated by minimal machines

^○Hitoshi Asano¹, Fumito Imura¹, Kazuhiro Koga¹, Sommawan Khumpuang^1,2, Shiro Hara^1,2 (MINIMAL¹, AIST²)

1:45 PM - 2:00 PM

[19p-E14-3] Electrical Characteristics of MOSFETs Fabricated by Full MINIMAL Equipment

^○Fumito Imura¹, Kazuhiro Koga¹, Hitoshi Asano¹, Sommawan Khumpuang^1,2, Shiro Hara^1,2 (MINIMAL¹, AIST²)

2:00 PM - 2:15 PM

[19p-E14-4] Cleanroom-Free Minimal Air Circulation System for PLAD (II)

^○Takashi Yajima¹, Masaharu Yasui¹, Sommawan Khumpuang^1,2, Hitoshi Maekawa^1,2, Shiro Hara^1,2 (MINIMAL¹, AIST²)

2:15 PM - 2:30 PM

[19p-E14-5] Development of Wafer Transfer System for Vacuum Process in the Minimalfab

^○Hitoshi Maekawa^1,3, Shinichi Imai^2,3, Sommawan Khumpuang^1,3, Shiro Hara^1,3 (AIST¹, TAZMO², MINIMAL³)

2:30 PM - 2:45 PM

[19p-E14-6] The Wafer Cleaning Process in the minimal

^○Shuuji Okuda¹, Sonoko Matsuda², Akihiro Goto², Sommawan Khumpuang^1,3, Shiro Hara^1,3 (MINIMAL¹, PRETECH², AIST³)

2:45 PM - 3:00 PM

[19p-E14-7] Cleaning process for contaminated wafer using MINIMAL Piranha Solution

^○Sonoko Matsuda^1,2, Akihiro Goto^1,2, Shuuji Okuda², Sommawan Khumpuang^2,3, Shiro Hara^2,3 (PRE-TECH CO.,LTD¹, MINIMAL², AIST³)

3:00 PM - 3:15 PM

[19p-E14-8] Exposure properties of a minimal Mask-aligner

^○Norio Umeyama¹, Yoshiki Inuzuka^1,2, Sommawan Khumpuang^1,3, Shiro Hara^1,3 (MINIMAL¹, Sanmei², AIST³)

3:15 PM - 3:30 PM

[19p-E14-9] Superimposing accuracy in Minimal Mask-less Exposure System

^○Yuuji Kitayama¹, Yousuke Tanaka^1,2, Ryouichi Irita^1,2, Kenji Miyake^1,2, Sommawan Khumpuang^1,3, Shiro Hara^1,3 (MINIMAL¹, PMT², AIST³)

3:30 PM - 3:45 PM

[19p-E14-10] Formation of slip dislocation by rapid heating in minimal heating equipment

^○Haruki Toonoe¹, Takashi Yajima¹, Yuuki Ishida^1,2, Shinichi Ikeda^1,2, Sommawan Khumpuang^1,2, Shiro Hara^1,2 (MIMINAL¹, AIST²)

Break 15:45〜16:00 (3:45 PM - 4:00 PM)

4:00 PM - 4:15 PM

[19p-E14-11] Silicon Thermal Oxidation Process using Minimal Focused Light Heating Furnace

^○Noriko Miura^1,2, Takeshi Aizawa^1,2, Takanori Mikahara², Takeshi Yamada^1,2, Yasuhiro Onishi^1,2, Yuuki Ishida^2,3, Shinichi Ikeda^2,3, Katsuhiko Nakato², Sommawan Khumpuang^2,3, Shiro Hara^2,3 (YONEKURA MFG. Co.,LTD¹, MINIMAL², AIST³)

4:15 PM - 4:30 PM

[19p-E14-12] Electric properties of thermal oxide formed by minimal resistance furnace

^○Katsuhiko Nakato¹, hitoshi Asano¹, Sinnosuke Suzuki^1,3, Shogo Matsuda^1,3, Ayami Yaginuma^1,3, Kiyohiko Morikawa^1,3, Masashi Hattori^1,3, Takanori Mikahara¹, Shinichi Ikeda^1,2, Sommawan Khumpuang^1,2, Shiro Hara^1,2 (MINIMAL¹, AIST², KOYO Thermo System Co.,Ltd³)

4:30 PM - 4:45 PM

[19p-E14-13] Minimal Spin-on dopant process

^○Kazuhiro Koga¹, Norio Umeyama^1,2, Fumito Imura¹, Hitoshi Asano¹, Haruki Toonoe¹, Sommawan Khumpuang^1,2, Shiro Hara^1,2 (MINIMAL¹, AIST²)

4:45 PM - 5:00 PM

[19p-E14-14] Minimal System of Micro-Plasma Etcher Equipment(II)

^○Hiroyuki Tanaka¹, Shizuka Nakano^1,2, Yoshiki Shimizu^1,2, Hisato Ogiso^1,2, Shinji Futagawa³, Hideaki Yoshioka³, Takahiro Fukuda³, Yoshinori Uchiyama³, Sommawan Khumpuang^1,2, Shiro Hara^1,2 (MINIMAL¹, AIST², Design Network³)

5:00 PM - 5:15 PM

[19p-E14-15] The depositional performance of the Al thin film in Minimal Sputtering System

^○Akihiko Katou^1,3, Hisato Ogiso^1,2, Shizuka Nakano^1,2, Yuuki Yabuta³, Sommawan Khumpuang^1,2, Shiro Hara^1,2 (MINIMAL¹, AIST², Seinan³)

5:15 PM - 5:30 PM

[19p-E14-16] Half-Inch Silicon CVD Reactor Using Concentrated Infrared Light Heater(2)

Ning Li¹, ^○Hitoshi Habuka¹, Shin-ichi Ikeda^{2, 3}, Yuuku Ishida^2、3, Shiro Hara^{2, 3} (Yokohama National Univ.¹, MINIMAL², AIST³)

5:30 PM - 5:45 PM

[19p-E14-17] Silicon Film Growth by the Minimal CVD Process

^○Shinichi Ikeda^1,2, Yuki Ishida^1,2, Takanori Mikahara¹, Katsuhiko Nakato¹, Hitoshi Habuka³, Khumpuang Sommawan^1,2, Shiro Hara^1,2 (MINIMAL¹, AIST², Yokohama National Univ.³)

5:45 PM - 6:00 PM

[19p-E14-18] Polish uniformity for Si and SiO₂ using a minimal CMP machine

^○Norio Umeyama¹, Kazutaka Shibuya^1,2, Yoshio Nakamura^1,2, Kouichiro Ichikawa², Sommawan Khumpuang^1,3, Shiro Hara^1,3 (MINIMAL¹, Fujikoshi Machinery², AIST³)

6:00 PM - 6:15 PM

[19p-E14-19] Room temperature ultrasonic bonding process for minimal wafer bonding system

^○Kazuhiro Noda¹, Seiya Nakai¹, Takanori Shuto², Keiichiro Iwanabe², Tanemasa Asano², Mutsuo Ogura³, Katsuhiko Nishida³ (adwelds¹, Kyushu Univ.², IR spec³)

6:15 PM - 6:30 PM

[19p-E14-20] Wafer thinning process with minimal back grinder

^○Suzuki Masaaki¹, Miura Osamu¹, Ito Noriko¹ (DISCO CORPORATION¹)

6:30 PM - 6:45 PM

[19p-E14-21] Development of a 3D-IC Tester for Minimal 3D-IC Fab

^○Naoya Watanabe¹, Kenji Kawano², Michiyuki Eto², Shiro Hara¹, Masahiro Aoyagi¹ (AIST¹, STK Technology²)

Session information

[19p-E14-1~21] 13.3 Si Process・Interconnect・MEMS・Integration