Performance of an E/D Inverter using Self-Aligned Planar Metal Double-Gate Four-Terminal LT Poly-Si TFTs

Hiroki Ohsawa

Presentation information

Oral presentation

13 Semiconductors » 13.4 Si wafer processing /MEMS/Integration technology

[13a-1C-1~10] 13.4 Si wafer processing /MEMS/Integration technology

Sun. Sep 13, 2015 9:00 AM - 11:45 AM 1C (135)

座長:河本直哉(山口大),松尾直人(兵庫県立大)

11:30 AM - 11:45 AM

△ [13a-1C-10] Performance of an E/D Inverter using Self-Aligned Planar Metal Double-Gate Four-Terminal LT Poly-Si TFTs

〇Hiroki Ohsawa¹, Akito Hara¹ (1.Tohoku Gakuin Univ.)

Keywords:TFT,Si,Poly-Si

An E/D inverter was fabricated using self-aligned planar metal double-gate four-terminal LT Poly-Si TFTs in which V_th control is possible. It was confirmed that the E/D inverter was successfully operated at V_DD=3.0 V and obtained good characteristics by V_th control.