[14a-4C-1~10] 13.3 Insulator technology

▼ [14a-4C-5] Fabrication and MOS interface properties of ALD AlYO3/GeOx/Ge gate stacks with plasma post oxidation

〇(M2)Mengnan Ke¹, Xiao Yu¹, Rui Zhang¹, Jian Kang¹, Chih-Yu Chang¹, Mitsuru Takenaka¹, Shinichi Takagi¹ (1.Tokyo Univ.)

Keywords:Ge

As one of the promising gate stacks, Al₂O₃/GeO_x/Ge and HfO₂/Al₂O₃/GeO_x/Ge structures realized by PPO ^[1,2] have been shown to have EOT of 1 nm or thinner, and low D_it of ~10¹¹ eV^-1cm^-2. However, one of the remaining critical issues is a large amount of slow traps, attributable to any defects inside gate insulators ^[3-5]. It has been recently reported that Y-doped GeO_x interface layers fabricated by sputtering can provide the superior MOS interface properties small hysteresis and low D_it.^[6-8] In this study, thus, we study the effect of ALD AlYO₃ layers, replacing Al₂O₃ in the PPO process, on the MOS interface properties including slow traps.