[14a-4C-1~10] 13.3 Insulator technology

▲ [14a-4C-6] [Young Scientist Presentation Award Speech] Interface-aware high-k dielectric designing for deep sub-nm EOT Ge gate stack

〇Cimang Lu^1,2, Choong Hyun Lee^1,2, Tomonori Nishimura^1,2, Akira Toriumi^1,2 (1.The Univ. of Tokyo, 2.JST-CREST)

Keywords:Germanium,High-k,Interface

Intensive investigation has been done on the gate stack formation on Ge and prominent interface passivation has been demonstrated by high quality GeO₂-based dielectrics. However, it is still challenging to achieve deep sub-nm EOT with maintaining good interface because the use of a high-k dielectric layer might also degrade the interface. In this work, we provide a high-k dielectric designing strategy, which can help us to find the interface aware high-k on Ge. As an example, YScO₃/Y-GeO₂/Ge stack is demonstrated with good interface and EOT scalability.