[14p-1C-1~16] 13.4 Si wafer processing /MEMS/Integration technology

△ [14p-1C-3] Effect of High-Aspect-Ratio-Via Formation on Transistor Performance in Via-last Backside-via Process for 3D IC

〇Yohei Sugawara¹, Hisashi Kino², Takafumi Fukushima^1,3, Kang-Wook Lee³, Mitsumasa Koyanagi³, Tetsu Tanaka^1,4 (1.Dept. of Bioengineering and Robotics, Tohoku Univ., 2.FRIS, Tohoku Univ., 3.NICHe, Tohoku Univ., 4.Dept. of Biomedical Engineering, Tohoku Univ.)

Keywords:3D IC,Charge up,Plasma