10:15 〜 10:30
▲ [15a-2T-6] Electrostatically Controlled P-I-N Junction in Graphene Nanoribbon Devices
キーワード：Graphene P-I-N junction
The power dissipation issue of the conventional Field Effect Transistors (FETs) is getting exceedingly serious, due to the off-state leakage power. Alternative devices based on new principles of physics have to be explored. One of the most promising alternative device is the Tunneling Field Effect Transistor (TFET). By exploiting the band-to-band tunneling (BTBT) phenomena, TFETs can achieve a subthreshold slope (SS) much lower than that for conventional FETs. However, as TFETs suffer from low ION current, and researchers now seek an appropriate material that can fulfill the requirements for high performance TFETs. Simulation studies have shown that graphene nanoribbon (GNR) based devices are capable of reaching far below the FET SS limit for switching by using BTBT [1,2]. The TFET structure consists of a P-I-N (p-type, intrinsic, n-type) junction, in which a gate terminal controls the electrostatic potential of the intrinsic region. Here we present the experimental study of electrostatically defined P-I-N junctions fabricated on CVD single layer graphene using the conventional electron beam lithography (EBL).
The schematic device structure is illustrated in Fig. 1a. First, source-drain electrodes are fabricated by using the lift-off technique. Then, EBL is used to pattern the GNR. High-resolution negative resist (hydrogen silsesquioxane, HSQ) and oxygen reactive ion etching are used to realize the ~22 nm wide GNR shown in Fig. 1b. Finally, two top gates are fabricated to realize the P and N-regions electrostatically. High-resolution positive resist (SML100) is used to fabricate these top gates by the lift-off technique. Figure 1c shows the back gate modulation at T = 4.8 K for the device with a 45 nm wide GNR and 35 nm top gate separation (the intrinsic region). A remarkable change of the transport gap is observed by decreasing the temperature from 300 K to 4.8 K (see Fig. 1d-g). In Figure 1g four clearly defined regions that correspond to the configuration of N-I-N, P-I-N, P-I-P and N-I-P. Details about other devices, and the effect of the back gate and the doping level on the source drain current will be presented in the conference.
The schematic device structure is illustrated in Fig. 1a. First, source-drain electrodes are fabricated by using the lift-off technique. Then, EBL is used to pattern the GNR. High-resolution negative resist (hydrogen silsesquioxane, HSQ) and oxygen reactive ion etching are used to realize the ~22 nm wide GNR shown in Fig. 1b. Finally, two top gates are fabricated to realize the P and N-regions electrostatically. High-resolution positive resist (SML100) is used to fabricate these top gates by the lift-off technique. Figure 1c shows the back gate modulation at T = 4.8 K for the device with a 45 nm wide GNR and 35 nm top gate separation (the intrinsic region). A remarkable change of the transport gap is observed by decreasing the temperature from 300 K to 4.8 K (see Fig. 1d-g). In Figure 1g four clearly defined regions that correspond to the configuration of N-I-N, P-I-N, P-I-P and N-I-P. Details about other devices, and the effect of the back gate and the doping level on the source drain current will be presented in the conference.