2015年 第76回応用物理学会秋季学術講演会

講演情報

一般セッション(口頭講演)

11 超伝導 » 11.5 接合,回路作製プロセスおよびデジタル応用

[15p-4B-1~7] 11.5 接合,回路作製プロセスおよびデジタル応用

2015年9月15日(火) 13:00 〜 14:45 4B (431-2)

座長:田中 雅光(名大)

13:15 〜 13:30

[15p-4B-2] Design Methodology for Very-Large-Scale-Integration of Adiabatic Quantum-Flux-Parametron Logic Superconductor Circuits

〇(P)Christopher Ayala1, Naoki Takeuchi1, Qiuyun Xu1, Yuki Murai1, Yuki Yamanashi1, Thomas Ortlepp1,2, Nobuyuki Yoshikawa1 (1.Yokohama Nat. Univ., 2.CiS Research Inst.)

キーワード:superconductor,vlsi,adiabatic quantum-flux-parametron

Novel computing devices bring forth the need to re-evaluate and potentially develop new systematic methodologies that enable their large-scale integration of complex circuits and systems. Adiabatic quantum-flux-parametron (AQFP) logic is an emerging technology in superconducting electronics that shows promise towards building extremely energy efficient computing systems with bit energies approaching 100kBT. Circuits such as an 8-bit Kogge-Stone parallel prefix carry look-ahead adder consisting of more than 1,000 Josephson junctions have already been demonstrated. Additionally, the operation of quantum-flux-latches (QFLs), compatible with AQFP logic circuits as a basic memory element, has also been experimentally confirmed. To continue moving towards very-large-scale-integration (VLSI), it is necessary to carefully and systematically abstract the low-level physics from the logic-level design of VLSI AQFP systems. In this talk, we describe the development of an AQFP cell library as a collection logic building blocks used to construct a digital circuit. The cell library includes logic-level models using a combination of finite-state machines and transport delay parameters to simulate logic functionality and impact of long AC power-clock bias lines used to excite AQFP gates. Such an approach will provide invaluable design and simulation flows for developing more complex VLSI AQFP circuits and ensure their critical timing closure.