[16a-1C-1~11] 13.5 デバイス／集積化技術

▲ [16a-1C-7] On the Device Design for Steep Slope Negative Capacitance FET (NCFET) Toward Sub-0.2V operation

〇Masaharu Kobayashi¹, Toshiro Hiramoto¹ (1.IIS, The Univ. of Tokyo)

キーワード：transistor,negative capacitance,ferroelectric

Steep slope negative capacitance FET (NCFET) has been a promising candidate as new CMOS platform for future IoT technology. In this work, we have proposed an NCFET with ferroelectric HfO₂ thin film. We have provided device design guideline for hysteresis-free and highly energy-efficient NCFET at less than Vdd 0.2V to determine optimum ferroelectric material parameters.