The 77th JSAP Autumn Meeting, 2016

Presentation information

Oral presentation

13 Semiconductors » 13.5 Semiconductor devices and related technologies

[13p-B13-1~12] 13.5 Semiconductor devices and related technologies

Tue. Sep 13, 2016 1:45 PM - 5:00 PM B13 (Exhibition Hall)

Toshiaki Tsuchiya(Shimane Univ.), Yukinori Ono(Shizuoka Univ.)

2:30 PM - 2:45 PM

[13p-B13-4] Negative Capacitance as a Performance Booster for Tunnel FET

Masaharu Kobayashi1, Kyungmin Jang1, Nozomu Ueyama1, Toshiro Hiramoto1 (1.IIS, Univ. of Tokyo)

Keywords:negative capacitance, tunnel FET, energy efficiency

Tunnel FET and Negative capacitance FET have been independently studied so far, however, there is an opportunity to combine these two devices and obtain super steep subthreshold slope. In this work, we propose a hybrid device architecture, Negative capacitance tunnel FET, where band-to-band tunneling is enhanced by channel potential amplification by negative capacitance. We build simulation method, design NCTFET and then benchmark its energy efficiency.