The 77th JSAP Autumn Meeting, 2016

Presentation information

Poster presentation

13 Semiconductors » 13.3 Insulator technology

[16a-P4-1~8] 13.3 Insulator technology

Fri. Sep 16, 2016 9:30 AM - 11:30 AM P4 (Exhibition Hall)

9:30 AM - 11:30 AM

[16a-P4-2] Characterization of Silicon Oxide Gate Dielectric layers Prepared at low temperatures Using Atmospheric Pressure Plasma Enhanced CVD

〇(M1)Yuichiro Kimoto1, Shogo Tamaki1, Koji Terawaki1, Kohei Kamada1, Hiromasa Ohmi1, Hiroaki Kakiuchi1, Kiyoshi Yasutake1 (1.Osaka Univ.)

Keywords:plasma enhanced CVD, gate dielectric layers, silicon oxide thin films