2016年第63回応用物理学会春季学術講演会

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10 スピントロニクス・マグネティクス » 10.3 GMR・TMR・磁気記録技術

[20a-W241-1~12] 10.3 GMR・TMR・磁気記録技術

2016年3月20日(日) 09:00 〜 12:15 W241 (西2・3号館)

小山 知弘(東大)

12:00 〜 12:15

[20a-W241-12] Vertical spin electric double layer transistor

寺田 博1、Anh Le Duc1、大矢 忍1、岩佐 義宏1、田中 雅明1 (1.東大院工)

キーワード:spin MOSFET,GaMnAs,ferromagnetic semiconductor

A spin metal-oxide-semiconductor field-effect transistor (spin MOSFET) is one of the promising devices for future electronics. In the spin MOSFET, the drain-source current IDS is modulated by both electric field and magnetization configurations. In previous studies, conventional planer spin MOSFET devices have been studied; however, the magnetoresistance (MR) ratios were very small. Recently, we have proposed a vertical spin MOSFET structure composed of epitaxially grown very thin channel sandwiched between ferromagnetic source/drain, which is preferable for the spin-dependent transport. In our previous study, IDS was modulated by 60% with MR and was modulated by 0.5% with a gate electric field. In this study, to obtain a larger IDS modulation ratio, we fabricated a vertical spin electric double layer transistor (vertical spin EDLT) structure, which consists of GaMnAs-based mesa diodes, a gate electrode, and ionic liquid. We reduced the size of the device compared with the one in our previous study to decrease the leak current which flows deeply inside from the surface of the mesas where the modulation of the potential with a gate electric field is weak. In addition, we applied the gate electric field by using ionic liquid, which is preferable to apply higher electric field.
We grew a heterostructure composed of Ga0.95Mn0.05As (9.2 nm)/ GaAs (11 nm)/ Ga0.95Mn0.05As (10 nm)/ GaAs: Be (100 nm) on a p+ GaAs (001) substrate by low-temperature molecular beam epitaxy. After the growth, we fabricated elongated shaped mesas with the size of 500 nm × 50 μm and the comb-shaped drain electrode which is connected to the top of the thirty mesa diodes. The substrate was used as a source electrode. The gate electrode was deposited on the insulating film placed beside the mesa diodes. The gate electrode and the mesa diodes were covered with electrolyte (DEME-TFSI). By applying a gate-source voltage VGS, the potential at the surface of the mesas is modulated. As a result, IDS is modulated by VGS. The obtained IDS decreased with increasing VGS, and the modulation ratio reaches 17.6% when VDS = 10 mV, at 3.8 K. This is much higher than that obtained in the previous report on the vertical spin-MOSFET. We measured the tunnel magnetoresistance (TMR) varying the in-plane magnetic field angle. We found unexpected behavior that the anisotropy of the TMR changes with VGS. In the presentation, we discuss the origin of the change of the magnetic anisotropy induced by the gate electric field.