The 63rd JSAP Spring Meeting, 2016

Presentation information

Oral presentation

15 Crystal Engineering » 15.6 Group IV Compound Semiconductors (SiC)

[20p-H101-1~21] 15.6 Group IV Compound Semiconductors (SiC)

Sun. Mar 20, 2016 1:15 PM - 7:00 PM H101 (H)

Masashi Kato(NITech), Mitsuo Okamoto(AIST), Mitsuru Sometani(Fuji Electric)

3:30 PM - 3:45 PM

[20p-H101-9] Proposal of local DLTS by super-higher-order scanning nonlinear dielectric microscopy and its application for evaluation of SiO2/SiC interface

Norimichi Chinone1, Ryoji Kosugi2, Yasunori Tanaka3, Shinsuke Harada2, Hajime Okumura2, Yasuo Cho1 (1.Tohoku Univ., 2.AIST, 3.Government of Japan)

Keywords:MOS interface,Scanning Probe Microscopy,DLTS

Techniques for evaluating MOS interface of SiC is indespensable to enhance SiC device charecteristics. In this study, local DLTS using super-higher-order scanning nonlinear dielectric microscopy (SHO-SNDM), which is one of SPM family, will be proposed. We will show an method for analyzing transient capacitance responses and some results obtained from SiC wafers with 45-nm-thick thermal oxide layer.