The 63rd JSAP Spring Meeting, 2016

Presentation information

Oral presentation

13 Semiconductors » 13.5 Semiconductor devices and related technologies

[20p-S422-1~18] 13.5 Semiconductor devices and related technologies

Sun. Mar 20, 2016 1:45 PM - 6:30 PM S422 (S4)

Keiji Ikeda(TOSHIBA), Jiro Ida(Kanazawa Inst. of Tech.)

3:00 PM - 3:15 PM

[20p-S422-6] Study on Steep Slope Switching in SOI-FETs using Negative Capacitance in Ferroelectric HfO2 Insulators: Importance on Design of BOX Thickness

Hiroyuki Ota1,3, Shinji Migita1,3, Koichi Fukuda1, Junichi Hattori1, Akira Toriumi2,3 (1.AIST, 2.Univ. of Tokyo, 3.CREST, JST)

Keywords:steep slope,negative capacitance,ferroelectric

MOSFETs with the ferroelectric gate insulator have been paid much attention as a steep subthreshold swing (SS) FETs. In this paper, we investigate a guideline for attaining the SS<60 mV/decade in silicon-on-insulator (SOI) MOSFETs based on TCAD simulation. As a result, we address importance of the ultrathin BOX.