[6a-C13-1~12] 3.15 Silicon photonics

[6a-C13-10] Investigation for low latency linear optics multiple bit input AND circuits

〇Shota Kita^1,2, Kengo Nozaki^1,2, Takumi Egawa³, Tohru Ishihara³, Akihiko Shinya^1,2, Masaya Notomi^1,2 (1.NTT Nanophotonics Center, 2.NTT BRL, 3.Kyoto Univ.)

Keywords:optical logic circuits, optical analogue computation, optoelectric circuits

We investigate multibit input AND circuits which is a preliminary model for low-latency optoelectric circuits based on optical analogue computation with electrical digital I/O. By applying linear optic AND gates with a bias input, we can minimize the number of devices and insertion loss with compensating the contrast. The latency of 128 bit AND could be reduced down to 1/10 compared to CMOS one.