Daisuke Yamane

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Speaker, Author, Co-Author

Tue. Mar 14, 2017 1:30 PM - 3:30 PM P3 (BP)

Poster presentation
| 13 Semiconductors
| 13.4 Si wafer processing /Si based thin film /Interconnect technology/ MEMS/ Integration technology

[14p-P3-1~19] 13.4 Si wafer processing /Si based thin film /Interconnect technology/ MEMS/ Integration technology

1:30 PM - 3:30 PM

[14p-P3-14] Young’s Modulus Evaluation of Electroplated Ti/Au Structures by Multi-layer Metal Technology (1)

〇Daisuke Yamane^1,4, Toshifumi Konishi², Teruaki Safu², Hideaki Nakajima^1,4, Minami Teranishi^1,4, Chun-Yi Chen^1,4, Tso-Fu Mark Chang^1,4, Masato Sone^1,4, Hiroshi Toshiyoshi^3,4, Kazuya Masu^1,4, Katsuyuki Machida^1,2,4 (1.Tokyo Tech., 2.NTT-AT, 3.The Univ. of Tokyo, 4.JST-CREST)

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