16:15 〜 16:30
[14p-B6-12] 常温で表面活性化接合したSi/GaAs界面の原子・電子構造
キーワード：表面活性化接合、シリコン/砒化ガリウム界面、透過電子顕微鏡
Si/GaAs interfaces were fabricated under a SAB condition at room temperature,1 with the substrates of B-doped (001) p-Si (with a carrier concentration of 2x1014 cm-3) and Si-doped n-GaAs (2x1016 cm-3) which was 5° off from (001) towards [110]. Parts of the SAB interfaces were then annealed at 473 K or 673 K for 1 minute. The Si surface and the GaAs one in a SAB interface were determined separately by plane-view TEM with the reflection of g = [220] for GaAs and that for Si, respectively.
At an as-bonded SAB interface, there was a partially-amorphized Si (a-Si) layer (~3nm thick) on the Si substrate, introduced during the surface activation process, and a thin Si oxide layer (less than ~0.5nm thick) existing at the GaAs/a-Si interface, introduced during the post-activation processes. The Si/a-Si interface was smooth, although the GaAs/a-Si interface was strained presumably due to dimples (~5nm in size) on the GaAs substrate introduced by Ar atoms, dumps (~20nm in size) at dislocations passing through the GaAs surface, and Si oxides on the Si substrate. Those strains were reduced by annealing according to the recrystallization of the a-Si layer, and this would result in the reduction of the interface resistance.1 It is therefore hypothesized that the interface resistance would be originated from the defects at the GaAs/a-Si interface, and the resistance might be reduced further by smoothing a surface on the GaAs substrate and/or removing the Si oxides on the a-Si layer, via optimization of the SAB condition.
[1] J. Liang, L. Chai, S. Nishida, M. Morimoto, N. Shigekawa, Jpn. J. Appl. Phys. 54 (2015) 030211.
At an as-bonded SAB interface, there was a partially-amorphized Si (a-Si) layer (~3nm thick) on the Si substrate, introduced during the surface activation process, and a thin Si oxide layer (less than ~0.5nm thick) existing at the GaAs/a-Si interface, introduced during the post-activation processes. The Si/a-Si interface was smooth, although the GaAs/a-Si interface was strained presumably due to dimples (~5nm in size) on the GaAs substrate introduced by Ar atoms, dumps (~20nm in size) at dislocations passing through the GaAs surface, and Si oxides on the Si substrate. Those strains were reduced by annealing according to the recrystallization of the a-Si layer, and this would result in the reduction of the interface resistance.1 It is therefore hypothesized that the interface resistance would be originated from the defects at the GaAs/a-Si interface, and the resistance might be reduced further by smoothing a surface on the GaAs substrate and/or removing the Si oxides on the a-Si layer, via optimization of the SAB condition.
[1] J. Liang, L. Chai, S. Nishida, M. Morimoto, N. Shigekawa, Jpn. J. Appl. Phys. 54 (2015) 030211.