The 64th JSAP Spring Meeting, 2017

Presentation information

Oral presentation

15 Crystal Engineering » 15.7 Crystal evaluation, impurities and crystal defects

[14p-F201-1~14] 15.7 Crystal evaluation, impurities and crystal defects

Tue. Mar 14, 2017 1:45 PM - 5:30 PM F201 (F201)

Koji Sueoka(Okayama Pref. Univ.), Satoshi Nakano(Kyushu Univ.)

4:00 PM - 4:15 PM

[14p-F201-9] DLTS measurements of p/n junction implanted with boron ions to n type Si substrate

Hiroki Wakimoto1, Haruo Nakazawa1, Takashi Matsumoto2, Yoichi Nabetani2 (1.Fuji Electric, 2.Yamanashi Univ.)

Keywords:pin diode, leakage current, Arrhenius plot

For pin diodes implanted and activated with boron ions into a high specific resistance n type Si substrate, it was found that there was a large difference in leakage current by the method of activation of the p layer. Since the trap state density in the vicinity of the p + / n - junction is supposed to be affected, we report on the DLTS mesurement results investigating what kinds of trap levels are formed.