[15p-P15-1~17] 13.5 Semiconductor devices and related technologies

[15p-P15-7] Write/Erase Endurance Stress Relaxation for 1Xnm TLC NAND Flash Memory

〇Yoshiaki Deguchi¹, Atsuro Kobayashi¹, Ken Takeuchi¹ (1.Chuo Univ.)

Keywords:NAND flash memory, TLC, Data-retention error

TLC NAND flash memory realizes low bit cost and large capacity by storing 3 bits per a cell. However, reliability is degraded with write/erase endurance stress and data-retention time. In this paper, the dependency of data-retention error on the interval of time between write/erase endurance stress and programming data is measured. Moreover, data-retention error is decreased by wear-leveling.