[16p-412-1~20] 13.5 Semiconductor devices and related technologies

[16p-412-1] Performance Improvement of C-TFET Circuits by Isoelectronic Trap Technology

〇Takahiro Mori¹, Hidehiro Asai¹, Junichi Hattori¹, Koichi Fukuda¹, Shintaro Otsuka¹, Yukinori Morita¹, Shin-ichi O'uchi¹, Hiroshi Fuketa¹, Shinji Migita¹, Wataru Mizubayashi¹, Hiroyuki Ota¹, Takashi Matsukawa¹ (1.AIST)

Keywords:Tunnel Field-Effect Transistors (TFETs), Complementary integrated circuits

Insufficient ON current is the biggest issue in tunnel field-effect transistors (TFETs). In particular, Si-TFETs are supposed to be unfavorable because tunneling probability is low in Si that is a kind of indirect gap semiconductors. To solve this problem, we have proposed isoelectronic trap (IET) technology to enhance the tunneling probability and demonstrated ON current enhancement in N-type Si-TFETs. In this presentation, we report ON current enhancement in P-type Si-TFETs and performance improvement in complementary integrated TFET circuits, those are inverters and ring oscillators, thanks to the IET technology.