[19p-432-1~8] Recent Progresses and Developments of Si Integrated Circuit Technologies with 3D Integrations

[19p-432-2] 3D Super Chip as a Key Technology in AI Era; Paradigm Shift and Business Strategy

〇Mitsumasa Koyanagi¹ (1.Tohoku Univ.)

Keywords:3D integration, heterogeneous integration, super chip

Novel 3D heterogeneous integration technologies using self-assembly have been developed to achieve high-throughput and high-precision multichip-to-wafer stacking. Many known good dies (KGDs) are simultaneously self-assembled on a carrier wafer with a high alignment accuracy making use of liquid surface tension. The self-assembled dies on the carrier are simultaneously transferred to another wafer or interposer wafer by electrostatically de-bonding the carrier wafer after Cu nano-pillar hybrid bonding of self-assembled dies. In addition, a new TSV formation methodology based on advanced Directed Self-Assembly (DSA) with nanocomposites consisting of nano metal particles and block-co-polymers is proposed. Cylindrical nano-ordered structures with metal which act as nano-TSV are formed in Si deep holes through phase separation of polystyrene-block-poly methyl methacrylate polymers (PS-b-PMMA). These new self-assembly technologies have been applied to develop a new heterogeneous nano-system-on-chip (3D Super Chip) including 3D neuromorphic chip which is the key device to support the IoT and AI era.