The 79th JSAP Autumn Meeting, 2018

Presentation information

Oral presentation

13 Semiconductors » 13.5 Semiconductor devices and related technologies

[20a-CE-1~12] 13.5 Semiconductor devices and related technologies

Thu. Sep 20, 2018 9:00 AM - 12:15 PM CE (Century Hall)

Takahiro Mori(AIST)

9:00 AM - 9:15 AM

[20a-CE-1] Physical Modeling for Fluctuation of Grain-Boundary Resistance in Polycrystalline Silicon

Michiru Hogyoku1, Takashi Izumida1, Hiroyoshi Tanimoto1, Nobutoshi Aoki1, Seiji Onoue1 (1.Toshiba Memory Corp.)

Keywords:poly-Si, resistance fluctuation, trap-assisted tunneling

Utilizing the trap-assisted tunneling model that can reproduce the grain-boundary(GB)-limited carrier mobility with negative temperature dependence, we have calculated fluctuation of the GB resistance in polycrystalline silicon. Near a threshold voltage condition, current fluctuation per one GB, corresponding to ±3σ, has been estimated to be one order magnitude, which is substantially larger than that for a single crystal.