Oral presentation

13 Semiconductors » 13.5 Semiconductor devices and related technologies

[20a-CE-1~12] 13.5 Semiconductor devices and related technologies

Thu. Sep 20, 2018 9:00 AM - 12:15 PM CE (Century Hall)

△：Presentation by Applicant for JSAP Young Scientists Presentation Award
▲：English Presentation
▼：Both of Above
No Mark：None of Above

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9:00 AM - 9:15 AM

[20a-CE-1] Physical Modeling for Fluctuation of Grain-Boundary Resistance in Polycrystalline Silicon

〇Michiru Hogyoku¹, Takashi Izumida¹, Hiroyoshi Tanimoto¹, Nobutoshi Aoki¹, Seiji Onoue¹ (1.Toshiba Memory Corp.)

9:15 AM - 9:30 AM

▼ [20a-CE-2] Reduced Subthreshold Slope Variability at High Temperature in Bulk and SOTB MOSFETs

〇(M2)Shuang Gao¹, Tomoko Mizutani¹, Kiyoshi Takeuchi¹, Masaharu Kobayashi¹, Toshiro Hiramoto¹ (1.IIS, Univ. of Tokyo)

9:30 AM - 9:45 AM

▲ [20a-CE-3] Reduced Drain-Induced-Barrier-Lowering (DIBL) Variability at High Temperature in Bulk and SOTB MOSFETs

〇(M2)Shuang Gao¹, Tomoko Mizutani¹, Kiyoshi Takeuchi¹, Masaharu Kobayashi¹, Toshiro Hiramoto¹ (1.IIS, Univ. of Tokyo)

9:45 AM - 10:00 AM

[20a-CE-4] Application of post-fabrication cell stability self-improvement using multiple stress technique to bulk SRAM cell array

〇Tomoko Mizutani¹, Kiyoshi Takeuchi¹, Takuya Saraya¹, Masaharu Kobayashi¹, Toshiro Hiramoto¹ (1.IIS, Univ. of Tokyo)

10:00 AM - 10:15 AM

[20a-CE-5] Design and analysis of virtually nonvolatile retention Flip-Flop using dual-mode inverters

〇Daiki Kitagata¹, Shuu'ichirou Yamamoto¹, Satoshi Sugahara¹ (1.Tokyo Inst. of Tech.)

10:15 AM - 10:30 AM

[20a-CE-6] Design and analysis of virtually nonvolatile retention SRAM using dual-mode inverters

〇Hayato Yoshida¹, Daiki Kitagata¹, Shuu'ichiro Yamamoto¹, Satoshi Sugahara¹ (1.FIRST,Tokyo inst. of Tech.)

10:45 AM - 11:00 AM

[20a-CE-7] Parasitic resistance characterization of FinFETs doped by solid-diffusion of phosphorus

〇Takashi Matsukawa¹, Takahiro Mori¹, Yoshihiro Sawada², Yohei Kinoshita², Yongxun Liu¹, Meishoku Masahara¹ (1.AIST, 2.Tokyo Ohka Kogyo)

11:00 AM - 11:15 AM

△ [20a-CE-8] Improvement of electrostatic gate-controlling for InAs nanowire vertical SGTs on Si

〇(M1)Hironori Gamo¹, Katsuhiro Tomioka¹, Junichi Motohisa¹ (1.Graduate School of IST and RCIQE, Hkkaido Univ.)

11:15 AM - 11:30 AM

[20a-CE-9] Sensitivity Characteristics of GaAsSb/InAs Nanowire Backward Diodes at 2.4 GHz

〇Tsuyoshi Takahashi^1,2, Kenichi Kawaguchi^1,2, Masaru Sato^1,2, Naoya Okamoto^1,2, Michihiko Suhara³ (1.Fujitsu, 2.Fujitsu Labs., 3.Tokyo Metro. Univ.)

11:30 AM - 11:45 AM

[20a-CE-10] Hole mobility enhancement in Ultra-smooth UTB-GeOI

〇WENHSIN CHANG¹, Toshifumi Irisawa¹, Hiroyuki Ishii¹, Noriyuki Uchida¹, Tatsuro Maeda¹ (1.AIST)

11:45 AM - 12:00 PM

▼ [20a-CE-11] Impact of SiGe Layer Thickness in Starting Substrates on Properties of Ultrathin Body Ge-on-insulator pMOSFETs fabricated by Ge Condensation

〇(DC)KwangWon Jo¹, WuKang Kim¹, Mitsuru Takenaka¹, Takagi Shinichi¹ (1.The university of Tokyo)

12:00 PM - 12:15 PM

[20a-CE-12] Demonstration of Ultralow (<10^-20 A/um) Off Leakage Current In-Zn-O Channel Transistor with EOT of 6.2nm

〇Nobuyoshi Saito¹, Tomoaki Sawabe¹, Junji Kataoka¹, Ueda Tomomasa¹, Tezuka Tsutomu¹, Ikeda Keiji¹ (1.Toshiba Memory Corp.)

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