[20p-212B-1~14] 11.4 Analog applications and their related technologies

[20p-212B-13] Cryo-packaging for Josephson voltage standard chip with reduced thermal stress

〇Hirotake Yamamori¹, Michitaka Maruyama¹, Yasutaka Amagai¹, Takeshi Shimazaki¹ (1.AIST)

Keywords:voltage standard, thermal stress, packaging technology

We have developed voltage standard using Josephson junction arrays. While good thermal contact is necessary to cool the device having huge power consumption by a cryocooler, we propose an easy and reliable way to mount the chip to a cryocooler with low cost. A numerical simulation suggests that slits fabricated in Cu plate reduces a thermal stress in a chip to about half. It is also shown that the temperature rise and nonuniformity of the temperature in a chip area won't be a problem. The different advantage has been also revealed when the chip has been actually mounted by this way, that will be also introduced on the day.