[20p-212B-1~14] 11.4 Analog applications and their related technologies

[20p-212B-14] Study of cryo-packaging for Josephson voltage standard chip using supersonic solder

〇Michitaka Maruyama¹, Hirotake Yamamori¹, Takeshi Shimazaki¹, Yasutaka Amagai¹ (1.AIST)

Keywords:Josephson voltage standard, cryo-packaging, supersonic solder

In cryo-packaging of our Josephson voltage standard chips, there is a problem that the voids appeared in the InSn solder layer degrade the thermal contact, causing the increase of the chip temperature due to Joule heat of the chips. It is considered that the vapor of the flux used to form the solder layer results in the voids. In this study, we attempted to form the solder layer without the flux by using supersonic-soldering method. The results of the observation using a scanning acoustic microscope (SAM) indicated that the area ratio of the voids decreased from approximately 78 % to approximately 34 %.