[18p-B11-1~14] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

△ [18p-B11-3] Data of "PN-Body-Tied SOI-FET" manufactured using 65 nm thin BOX FDSOI

〇Keita Daimatsu¹, Jiro Ida¹, Takuya Yamada¹, Takayuki Mori¹ (1.Kanazawa Inst.)

Keywords:ultra low power devices, steep slope devices, SOI-FET

We have proposed "PN-Body-Tied (PNBT) SOI-FET" as a new device to realize ultra-low power consumption LSI and have reported a steep SS less than 1mV / dec. So far, PNBT SOI-FET was fabricated by 200 nm SOI technology. In this stady, we made a PNBT SOI-FET for the first time by using 65 nm thin BOX FDSOI process and confirmed a steep SS below 1 mV / dec.