The 80th JSAP Autumn Meeting 2019

Presentation information

Print

Oral presentation

11 Superconductivity » 11.5 Junction and circuit fabrication process, digital applications

[20p-C213-1~14] 11.5 Junction and circuit fabrication process, digital applications

Fri. Sep 20, 2019 1:15 PM - 5:00 PM C213 (C213)

Yoshinao Mizugaki(UEC), Yuki Yamanashi(Yokohama Natl. Univ.)

3:45 PM - 4:00 PM

[20p-C213-10] Design and error-rate testing of an area-reduced SFQ-NOT gate

〇Koki Yamazaki1, Hiroshi Shimada1, Yoshinao Mizugaki1 (1.Univ. of Electro-Comm.)

Keywords:single flux quantum, error rate