Technology Platform Development of Multichip-to-Wafer3D Integration (2)<br />- SiO<sub>2</sub>LinerTechnology for Low TemperatureTSV Process -

Rui Liang; Sungho Lee; Yuki Miwa; Hisashi Kino; Hisashi Fukushima; Tetsu Tanaka

Presentation information

Oral presentation

13 Semiconductors » 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[10p-S221-1~10] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

Sun. Mar 10, 2019 1:45 PM - 5:00 PM S221 (S221)

Toshifumi Irisawa(AIST), Ken Uchida(Univ. Tokyo)

4:30 PM - 4:45 PM

▼ [10p-S221-9] Technology Platform Development of Multichip-to-Wafer3D Integration (2)
- SiO₂LinerTechnology for Low TemperatureTSV Process -

〇(M1)Rui Liang¹, Sungho Lee², Yuki Miwa³, Hisashi Kino⁴, Hisashi Fukushima², Tetsu Tanaka^1,2 (1.Grad. Sch. of Biomedical Engineering, Tohoku Univ., 2.Grad. Sch. of Engineering, Tohoku Univ., 3.Sch. of Engineering Tohoku Univ., 4.FRIS, Tohoku Univ.)

Keywords:TSV, Multichip-to-Wafer

Presentation information

[10p-S221-1~10] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

▼ [10p-S221-9] Technology Platform Development of Multichip-to-Wafer3D Integration (2)- SiO2LinerTechnology for Low TemperatureTSV Process -

▼ [10p-S221-9] Technology Platform Development of Multichip-to-Wafer3D Integration (2)
- SiO₂LinerTechnology for Low TemperatureTSV Process -