[10p-S221-1~10] 13.5 デバイス／配線／集積化技術

▼ [10p-S221-9] Technology Platform Development of Multichip-to-Wafer3D Integration (2)
- SiO₂LinerTechnology for Low TemperatureTSV Process -

〇(M1)Rui Liang¹、Sungho Lee²、Yuki Miwa³、Hisashi Kino⁴、Hisashi Fukushima²、Tetsu Tanaka^1,2 (1.Grad. Sch. of Biomedical Engineering, Tohoku Univ.、2.Grad. Sch. of Engineering, Tohoku Univ.、3.Sch. of Engineering Tohoku Univ.、4.FRIS, Tohoku Univ.)

キーワード：TSV, Multichip-to-Wafer