[11p-W331-1~12] 3.15 Silicon photonics

[11p-W331-2] Investigation for multiple input Si wire Ψ gates towards ultralow-latency multiple bit operation

〇Shota Kita^1,2, Akihiko Shinya^1,2, Kengo Nozaki^1,2, Masaya Notomi^1,2 (1.NTT Nanophotonics Center, 2.NTT BRL)

Keywords:photonic computng, logic operations, multiple mode interference waveguides

We investigated multiple input Si wire Ψ gates towards higher performance operation functions including low-latency AND operations. Multiple input gates would be effective not only for shorter critical path, but also lower loss. We have optimized a 4+1 input Ψ gate with utilizing multi-parametric optimization, and simulated 4-bit AND operation. As the result, the net loss has been evaluated to be ~0.9 dB which is already 2.1 dB lower than the previous limit. There are no reports on such shorter and lower loss multi-port interference system, and we believe it would be one of key technologies contributing for the development of lower-latency photonic computing circuits and architecture.