Yusaku Shiotsu

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Speaker, Author, Co-Author

Fri. Sep 11, 2020 8:30 AM - 11:45 AM Z09

Oral presentation
| 13 Semiconductors
| 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[11a-Z09-1~12] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

11:00 AM - 11:15 AM

[11a-Z09-10] Design and analysis of 8kB SRAM macro using a new ultralow-voltage-retention architecture

〇Yusaku Shiotsu¹, Daiki Kitagata¹, Shuu'ichirou Yamamoto¹, Satoshi Sugahara¹ (1.FIRST, Tokyo Inst. of Tech.)