[11a-Z09-1~12] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[11a-Z09-11] Effects of shutdown-allowed time distribution on power reduction efficiency of power gating for retention SRAMs

〇Hayato Yoshida¹, Daiki Kitagata¹, Shuu'ichiro Yamamoto¹, Satoshi Sugahara¹ (1.FIRST, Tokyo Inst. of Tech)

Keywords:Power gating, SRAM, Low static power