Oral presentation

[11a-Z09-1~12] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

Fri. Sep 11, 2020 8:30 AM - 11:45 AM Z09

Kensuke Ota(Kioxia), Osamu Nakatsuka(Nagoya Univ.)

△：Presentation by Applicant for JSAP Young Scientists Presentation Award
▲：English Presentation
▼：Both of Above
No Mark：None of Above

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8:30 AM - 8:45 AM

[11a-Z09-1] Analysis of Saturation Effect at Low Vds appearing in PN-Body Tied SOI-FET

〇Hiroki Ito¹, Jiro Ida¹, Takayuki Mori¹ (1.Kanazawa Inst. of Tech)

8:45 AM - 9:00 AM

▲ [11a-Z09-2] Improvement of electrical characteristics of junctionless transistor with BF₂⁺ implanted poly-Si channel by boron segregation and fluorine passivation

〇(D)Minju Ahn¹, Takuya Saraya¹, Masaharu Kobayashi¹, Toshiro Hiramoto¹ (1.Institute of Industrial Science, The University of Tokyo)

9:00 AM - 9:15 AM

▲ [11a-Z09-3] GAA p-type poly-Si junctionless nanowire transistor with ideal subthreshold slope

〇(D)Minju Ahn¹, Takuya Saraya¹, Masaharu Kobayashi¹, Toshiro Hiramoto¹ (1.Institute of Industrial Science, The University of Tokyo)

9:15 AM - 9:30 AM

[11a-Z09-4] Improvement of Ge MOS interfacial quality through HI plasma treatment

〇WENHSIN CHANG¹, Toshifumi Irisawa¹, Hiroyuki Ishii¹, Tatsuro Maeda¹ (1.AIST)

9:30 AM - 9:45 AM

△ [11a-Z09-5] Demonstration of Surrounding Gate Vertical-Channel FET with Gate Length of 40 nm Using BEOL Process Compatible In-Al-Zn Oxide Channel

〇Hirokazu Fujiwara¹, Yuta Sato¹, Nobuyoshi Saito¹, Tomomasa Ueda¹, Keiji Ikeda¹ (1.Kioxia Corp.)

9:45 AM - 10:00 AM

▼ [11a-Z09-6] Improvement of current transportation ability of ZnO-nanoparticle-based thin-film transistors by diffusion type Ga-doping process

〇(D)MD MARUFUL ISLAM¹, Toshiyuki Yoshida¹, Yasuhisa Fujita¹ (1.Shimane University)

10:15 AM - 10:30 AM

▲ [11a-Z09-7] 3D Integration of RRAM Array with Oxide Semiconductor FET for In-Memory Computing

〇(P)Jixuan Wu¹, Fei Mo¹, Takuya Saraya¹, Toshiro Hiramoto¹, Masaharu Kobayashi¹ (1.IIS, Univ. of Tokyo)

10:30 AM - 10:45 AM

[11a-Z09-8] Data Control Technique based on Image Spatial Locality and Color Pattern for 3D-TLC NAND Flash Memory

〇Chihiro Matsui¹, Ken Takeuchi¹ (1.Univ. Tokyo)

10:45 AM - 11:00 AM

[11a-Z09-9] Design and analysis of a new ultralow-voltage-retention SRAM cell

〇Daiki Kitagata¹, Hayato Yoshida¹, Yusaku Shiotsu¹, Shuu'ichirou Yamamoto¹, Satoshi Sugahara¹ (1.Tokyo Inst. of Tech.)

11:00 AM - 11:15 AM

[11a-Z09-10] Design and analysis of 8kB SRAM macro using a new ultralow-voltage-retention architecture

〇Yusaku Shiotsu¹, Daiki Kitagata¹, Shuu'ichirou Yamamoto¹, Satoshi Sugahara¹ (1.FIRST, Tokyo Inst. of Tech.)

11:15 AM - 11:30 AM

[11a-Z09-11] Effects of shutdown-allowed time distribution on power reduction efficiency of power gating for retention SRAMs

〇Hayato Yoshida¹, Daiki Kitagata¹, Shuu'ichiro Yamamoto¹, Satoshi Sugahara¹ (1.FIRST, Tokyo Inst. of Tech)

11:30 AM - 11:45 AM

[11a-Z09-12] Proposal of a new ultralow-voltage-retention Flip-Flops

〇Kenichiro Takiguchi¹, Daiki Kitagata¹, Tsubasa Matsuzaki¹, Shuu'ichirou Yamamoto¹, Satoshi Sugahara¹ (1.FIRST, Tokyo Inst. of Tech)

Oral presentation

[11p-Z09-1~15] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

Fri. Sep 11, 2020 12:45 PM - 5:15 PM Z09

Gento Yamahata(NTT BRL), Munehiro Tada(NEC), Kazuhiko Endo(AIST)

△：Presentation by Applicant for JSAP Young Scientists Presentation Award
▲：English Presentation
▼：Both of Above
No Mark：None of Above

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12:45 PM - 1:00 PM

[11p-Z09-1] [Award Ceremony] The 11th Silicon Technology Division Award

〇Ken Uchida¹ (1.Silicon Technology Division)

1:00 PM - 1:30 PM

[11p-Z09-2] [The 11th Silicon Technology Division Award Speech] 25-Gb/s × Four-Channel Chip-Scale Optical Receiver Operating at up to 85 °C with a Temperature-Compensation Function

〇Daisuke Okamoto¹, Yasuyuki Suzuki¹, Yasuhiko Hagihara², Mitsuru Kurihara², Takahiro Nakamura¹, Kazuhiko Kurata² (1.PETRA, 2.AIOcore)

1:30 PM - 2:00 PM

[11p-Z09-3] [The 11th Silicon Technology Division Award Speech] Electron Aspirator using Electron-Electron Scattering in Nanoscale Silicon

〇Yukinori Ono^1,2, Himma Firdaus², Tokinobu Watanabe¹, Masahiro Hori^1,2, Daniel Moraru^1,2, Yasuo Takahashi³, Akira Fujiwara⁴ (1.RIE Shizuoka Univ., 2.GSST Shizuoka Univ., 3.Hokkaido Univ., 4.NTT BRL)

2:00 PM - 2:15 PM

[11p-Z09-4] [The 11th Silicon Technology Division Award Speech] Charge Pumping Under Spin Resonance in Si(100) Metal-Oxide-Semiconductor Transistors

〇Masahiro Hori¹, Yukinori Ono¹ (1.Shizuoka Univ.)

2:15 PM - 2:30 PM

[11p-Z09-5] [The 11th Silicon Technology Division Award Speech] Bilayer tunnel field effect transistor with oxide-/group-IV semiconductors

〇Kimihiko Kato^1,2, Hiroaki Matsui¹, Hitoshi Tabata¹, Mitsuru Takenaka¹, Shinichi Takagi¹ (1.Univ. of Tokyo, 2.AIST)

2:30 PM - 2:45 PM

[11p-Z09-6] Mechanism of Gate-Length Dependence of Quantum Dot Operation in Isoelectronic-Trap-Assisted Tunnel FETs

〇Shota Iizuka¹, Hidehiro Asai¹, Kimihiko Kato¹, Junichi Hattori¹, Koichi Fukuda¹, Takahiro Mori¹ (1.AIST)

2:45 PM - 3:00 PM

[11p-Z09-7] Tunneling Current through Doped Si-p/n Junction; Three-dimensional Simulation

〇(D)Sanghun Cho¹, Takashi Nakayama¹ (1.Chiba Univ.)

3:15 PM - 3:30 PM

[11p-Z09-8] Characterization of physically defined silicon quantum dot with tunnel-coupled charge sensor

〇Raisei Mizokuchi¹, Shimpei Nishiyama^1,2, Kimihiko Kato², Yongxun Liu², Takahiro Mori², Tetsuo Kodera¹ (1.Tokyo Tech., 2.AIST)

3:30 PM - 3:45 PM

[11p-Z09-9] Signal multiplexing for readout of quantum dot states on a single data line

〇Masaru Hirayama¹, Raisei Mizokuchi¹, Masahiro Tadokoro¹, Tetsuo Kodera¹ (1.Tokyo Tech)

3:45 PM - 4:00 PM

△ [11p-Z09-10] NISQ device with silicon qubits for large scale integration

〇Masahiro Tadokoro^1,2, Takashi Nakajima², Takashi Kobayashi², Kenta Takeda², Akito Noiri², Kaito Tomari¹, Seigo Tarucha², Tetsuo Kodera¹ (1.Tokyo Tech., 2.Riken)

4:00 PM - 4:15 PM

△ [11p-Z09-11] Understanding the Origin of Cryogenic 1/f Noise by Utilizing Cryo-CMOS

〇Hiroshi Oka¹, Takashi Matsukawa¹, Kimihiko Kato¹, Shota Iizuka¹, Wataru Mizubayashi¹, Kazuhiko Endo¹, Tetsuji Yasuda¹, Takahiro Mori¹ (1.AIST)

4:15 PM - 4:30 PM

[11p-Z09-12] Measurement of neutral electroless copper plating rate with QCM method

〇(M1)Tomoya Sawafuji¹, Osamu Sugiura¹ (1.Chiba Inst. of Tech.)

4:30 PM - 4:45 PM

[11p-Z09-13] Study of Cu Diffusion Barrier using Mn-doped Co film

〇(M2)Taro Matsudaira¹, Tomohiro Shimizu¹, Takeshi Ito¹, Shoso Shingubara¹ (1.Kansai Univ.)

4:45 PM - 5:00 PM

[11p-Z09-14] Structural analysis of ultrathin TaWN barriers with Cu(111) orientation control

〇Mayumi Takeyama¹, Masaru Sato¹, Mitsunobu Yasuda² (1.Kitami Inst. Technol., 2.Toray Research Center)

5:00 PM - 5:15 PM

[11p-Z09-15] Optical absorption factor analysis in actual reflectance measurementby Optical Interference Contactless Thermometer

〇Tatsuki Koyanagi¹, Yuri Mizukawa², Hiroaki Hanafusa², Seiichirou Higasi² (1.AdSM,Hiroshima Univ., 2.AdSE,Hiroshima univ.)

Sessions

13 Semiconductors » 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[11a-Z09-1~12] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[11a-Z09-1] Analysis of Saturation Effect at Low Vds appearing in PN-Body Tied SOI-FET

▲ [11a-Z09-2] Improvement of electrical characteristics of junctionless transistor with BF₂⁺ implanted poly-Si channel by boron segregation and fluorine passivation

▲ [11a-Z09-3] GAA p-type poly-Si junctionless nanowire transistor with ideal subthreshold slope

[11a-Z09-4] Improvement of Ge MOS interfacial quality through HI plasma treatment

△ [11a-Z09-5] Demonstration of Surrounding Gate Vertical-Channel FET with Gate Length of 40 nm Using BEOL Process Compatible In-Al-Zn Oxide Channel

▼ [11a-Z09-6] Improvement of current transportation ability of ZnO-nanoparticle-based thin-film transistors by diffusion type Ga-doping process

▲ [11a-Z09-7] 3D Integration of RRAM Array with Oxide Semiconductor FET for In-Memory Computing

[11a-Z09-8] Data Control Technique based on Image Spatial Locality and Color Pattern for 3D-TLC NAND Flash Memory

[11a-Z09-9] Design and analysis of a new ultralow-voltage-retention SRAM cell

[11a-Z09-10] Design and analysis of 8kB SRAM macro using a new ultralow-voltage-retention architecture

[11a-Z09-11] Effects of shutdown-allowed time distribution on power reduction efficiency of power gating for retention SRAMs

[11a-Z09-12] Proposal of a new ultralow-voltage-retention Flip-Flops

[11p-Z09-1~15] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[11p-Z09-1] [Award Ceremony] The 11th Silicon Technology Division Award

[11p-Z09-2] [The 11th Silicon Technology Division Award Speech] 25-Gb/s × Four-Channel Chip-Scale Optical Receiver Operating at up to 85 °C with a Temperature-Compensation Function

[11p-Z09-3] [The 11th Silicon Technology Division Award Speech] Electron Aspirator using Electron-Electron Scattering in Nanoscale Silicon

[11p-Z09-4] [The 11th Silicon Technology Division Award Speech] Charge Pumping Under Spin Resonance in Si(100) Metal-Oxide-Semiconductor Transistors

[11p-Z09-5] [The 11th Silicon Technology Division Award Speech] Bilayer tunnel field effect transistor with oxide-/group-IV semiconductors

[11p-Z09-6] Mechanism of Gate-Length Dependence of Quantum Dot Operation in Isoelectronic-Trap-Assisted Tunnel FETs

[11p-Z09-7] Tunneling Current through Doped Si-p/n Junction; Three-dimensional Simulation

[11p-Z09-8] Characterization of physically defined silicon quantum dot with tunnel-coupled charge sensor

[11p-Z09-9] Signal multiplexing for readout of quantum dot states on a single data line

△ [11p-Z09-10] NISQ device with silicon qubits for large scale integration

△ [11p-Z09-11] Understanding the Origin of Cryogenic 1/f Noise by Utilizing Cryo-CMOS

[11p-Z09-12] Measurement of neutral electroless copper plating rate with QCM method

[11p-Z09-13] Study of Cu Diffusion Barrier using Mn-doped Co film

[11p-Z09-14] Structural analysis of ultrathin TaWN barriers with Cu(111) orientation control

[11p-Z09-15] Optical absorption factor analysis in actual reflectance measurementby Optical Interference Contactless Thermometer

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Sessions

13 Semiconductors » 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[11a-Z09-1~12] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

▲ [11a-Z09-2] Improvement of electrical characteristics of junctionless transistor with BF2+ implanted poly-Si channel by boron segregation and fluorine passivation

▲ [11a-Z09-3] GAA p-type poly-Si junctionless nanowire transistor with ideal subthreshold slope

△ [11a-Z09-5] Demonstration of Surrounding Gate Vertical-Channel FET with Gate Length of 40 nm Using BEOL Process Compatible In-Al-Zn Oxide Channel

▼ [11a-Z09-6] Improvement of current transportation ability of ZnO-nanoparticle-based thin-film transistors by diffusion type Ga-doping process

▲ [11a-Z09-7] 3D Integration of RRAM Array with Oxide Semiconductor FET for In-Memory Computing

[11p-Z09-1~15] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

△ [11p-Z09-10] NISQ device with silicon qubits for large scale integration

△ [11p-Z09-11] Understanding the Origin of Cryogenic 1/f Noise by Utilizing Cryo-CMOS

Authenticate

▲ [11a-Z09-2] Improvement of electrical characteristics of junctionless transistor with BF₂⁺ implanted poly-Si channel by boron segregation and fluorine passivation