The 81st JSAP Autumn Meeting, 2020

Presentation information

Oral presentation

13 Semiconductors » 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[11a-Z09-1~12] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

Fri. Sep 11, 2020 8:30 AM - 11:45 AM Z09

Kensuke Ota(Kioxia), Osamu Nakatsuka(Nagoya Univ.)

9:30 AM - 9:45 AM

[11a-Z09-5] Demonstration of Surrounding Gate Vertical-Channel FET with Gate Length of 40 nm Using BEOL Process Compatible In-Al-Zn Oxide Channel

Hirokazu Fujiwara1, Yuta Sato1, Nobuyoshi Saito1, Tomomasa Ueda1, Keiji Ikeda1 (1.Kioxia Corp.)

Keywords:oxide semiconductor, vertical field effect transistor

We have successfully developed a surrounding gate vertical-channel FET with gate length of 40nm using BEOL process compatible In-Al-Zn-O channel, for the first time. Fabricated FETs exhibited both high mobility (~12cm2/Vs) and excellent cut off characteristics (S.S. = 130mV/dec.) even after annealing at 420 oC. In addition, it also indicated high reliability and achieved endurance over 1011 cycles. These results indicate that a great potential of surrounding gate short-channel vertical FET with an oxide-semiconductor channel as high performance BEOL transistor for 3D-LSI applications.