The 81st JSAP Autumn Meeting, 2020

Presentation information

Oral presentation

13 Semiconductors » 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[11a-Z09-1~12] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

Fri. Sep 11, 2020 8:30 AM - 11:45 AM Z09

Kensuke Ota(Kioxia), Osamu Nakatsuka(Nagoya Univ.)

9:00 AM - 9:15 AM

[11a-Z09-3] GAA p-type poly-Si junctionless nanowire transistor with ideal subthreshold slope

〇(D)Minju Ahn1, Takuya Saraya1, Masaharu Kobayashi1, Toshiro Hiramoto1 (1.Institute of Industrial Science, The University of Tokyo)

Keywords:Gate-all-around nanowire structure, Poly-Si junctionless transistor, Ideal subthreshold slope

In this work, we fabricated the gate-all-around (GAA) p-type poly-Si junctionless (JL) nanowire (NW) transistors, and observed excellent subthreshold characteristics close to ideal subthreshold slope (60mV/dec.) as well as high on/off current ratio (~1.2x108) and low off-current (<10-13A) thanks to improved fabrication processes as well as highly suppressed grain boundary defects. The origins will be discussed based on experimental results.