[9p-Z26-1~14] 9.3 Nanoelectronics

[9p-Z26-12] Fabrication and characterization of nanostructure-embedded Si MOSFET for nano-artifact-metrics

〇Shintaro Mizuno¹, Renpeng Lu¹, Katsumi Shimizu¹, Xiang Yin¹, Yosuke Ueba², Mikio Ishikawa², Mitsuru Kitamura², Morihisa Hoga³, Seiya Kasai¹ (1.RCIQE, Hokkaido Univ., 2.DNP, 3.AIST)

Keywords:semiconductor

Artifact metrics using physical features that cannot be replicated artificially are attracting attention as a secure authentication technology in environments where physical and cyber spaces merge. Nanostructure artifacts metrics based on resistive collapse phenomenon have high security performance. The challenge is to read out the microstructure. We have proposed a method to embed the nanostructures directly under the gate of a MOSFET to identify them electrically. In this study, a single nanostructured Si MOSFET has been fabricated and its electrical characteristics have been evaluated.