[13p-PA9-1~25] 13.7 Compound and power electron devices and process technology

[13p-PA9-6] Evaluation of electron trap behavior by voltage stress using GaN-MOS capacitor

〇Hideaki Matsuyama¹, Katsunori Ueno¹, Ryo Tanaka¹, Yuta Fukushima¹, Takuro Inamoto¹, Shinya Takashima¹ (1.Fuji Electric)

Keywords:GaN-MOS capacitor, GaOx interface layer, electron trap

In the SiO2/GaN-MOSFET the hysteresis occurred in the Vg-Id characteristics due to the positive voltage stress, and was related to the GaOx interface layer. It was presumed that electron traps at the SiO2/GaOx interface were the cause, and the trapped electron density by applying a stress voltage was investigated using a MOS capacitor. As a result, it was found that electrons were captured by the deep trap due to the positive voltage stress.