[11a-N205-1~11] CS.9 6.1 強誘電体薄膜、13.3 絶縁膜技術、13.5 デバイス／配線／集積化技術のコードシェアセッション

▲ [11a-N205-10] Role of GIDL Current for Efficient Erase Operation and Interfacial Layer Engineering for Low-Voltage Operation in HfO₂-based FeFET

Fei Mo¹、Jiawen Xiang¹、Xiaoran Mei¹、Yoshiki Sawabe¹、Takuya Saraya¹、Toshiro Hiramoto¹、Chun-Jung Su²、Vita Pi-Ho Hu³、〇Masaharu Kobayashi^1,4 (1.IIS, Univ. Tokyo、2.TSRI、3.Nat. Taiwan Univ.、4.d.lab, Univ. Tokyo)

キーワード：ferroelectric, memory

FeFET has been recently attracting attentions for its low-power, high-speed operation since CMOS compatible ferroelectric(FE)-HfO₂ was discovered [1]. 3D vertical NAND type structure has been used for high-density Flash memory and thus it is natural to consider the same structure for FeFET [2]. However, minority carrier generation can be slow in erase operation due to the floating body. To solve this problem, it is useful to utilize gate induced drain leakage (GIDL) current for erase operation [3]. But erase operation by GIDL current was not fully studied for FeFET yet. Another key challenge for FeFET is the operation voltage. Although FeFET is expected to operate at low-voltage, but the interfacial layer (IL) between FE-HfO₂ and Si channel prevents low-voltage operation and degrades reliability.