[12p-N304-1~14] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

△ [12p-N304-11] Study of TiN as barrier metal for W via on Cu interconnect

〇Genki Sawada¹, Masayuki Kitamura¹, Atsushi Kato¹, Hiroaki Matsuda¹, Koji Arita¹, Masayoshi Tagami¹, Yumi Nakajima¹, Atsushi Oga¹ (1.KIOXIA Corporation)

Keywords:Cu interconnect, W via, TiN barrier metal

Recently, large amounts of data are generated and will be increased explosively in the future. 3D flash memory can realize large capacity, high speed and low bit cost. In order to meet these device properties, process technologies for higher stacking and scaling have been developed, and interconnects scaling is one of important factors. In this presentation, we will clarify the problems caused by TiN barrier metal in high aspect ratio W via on narrow pitch Cu interconnect, and propose process solutions.