[12p-N403-1~14] 11.5 Junction and circuit fabrication process, digital applications

[12p-N403-9] Design of a Clockless Single Flux Quantum Logic Gate Alleviating the Input Timing Constraints

〇Taisei Fujisawa¹, Yuki Yamanashi¹, Nobuyuki Yoshikawa¹ (1.Yokohama National Univ.)

Keywords:SFQ circuit, clockless logic gate, clockless XOR gate