[17a-Z26-1~9] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[17a-Z26-7] Energy-efficient operation at energy minimum point for ultra-low-voltage-retention FF

〇Kenichiro Takiguchi¹, Yusaku Shiotsu¹, Tsubasa Matsuzaki¹, Shuu'ichirou Yamamoto¹, Satoshi Sugahara¹ (1.FIRST, Tokyo Inst. of Tech.)

Keywords:Power gating, Flip-Flop, Low power