[22p-A307-1~17] CS.7 6.1 強誘電体薄膜、13.3 絶縁膜技術、13.5 デバイス／配線／集積化技術のコードシェア

▼ [22p-A307-1] A Vertical Channel Ferroelectric/Anti-Ferroelectric FET with ALD InOx

〇Zhuo Li¹、Jixuan Wu¹、Xiaoran Mei¹、Xingyu Huang¹、Takuya Saraya¹、Toshiro Hiramoto¹、Takanori Takahashi²、Mutsunori Uenuma²、Yukiharu Uraoka²、Masaharu Kobayashi^1,3 (1.IIS., Univ. of Tokyo、2.NAIST、3.d.lab, Univ. of Tokyo)

キーワード：FeFET, AFeFET, Oxide semiconductor Channel

Ferroelectric FET (FeFET) has been a promising solution for high speed and low power with the use of CMOS-compatible Fe-HfO₂. Moreover, 3D vertical stack FeFETs can achieve more for high-density storage memory. Compared to poly-Si channel, oxide semiconductor (OS) channel has high mobility and no low-k interfacial layer. However, OS channel FeFET has an issue of weak erase. Program operation is easy to achieve because of the fast generation and supply of majority carriers. Low minority carrier concentration makes erase operation difficult to achieve. Previously, theoretical and experimental works show shorter L_g and thinner channel can achieve better memory window (MW). This helps to mitigate the weak erase issue by the electrostatic coupling between the body and source/drain. For 3D memory, ALD process is necessary for conformal deposition of OS channel material. Moreover, anti-ferroelectric (AFe)-HfO₂ gate insulator is also proposed instead of Fe-HfO₂. We think AFe-HfO₂ is a feasible approach for OS channel because the use of half-loop hysteresis only requires small net charge in anti-parallel polarization for erase operation. In this study, we fabricated 3D vertical channel FeFET and AFeFET with L_g=50nm. The MW >1V and >0.5V are confirmed respectively. Endurance and retention measurements are performed and reliable memory operation is confirmed. Erase state retention is improved by AFeFET thanks to the efficient erase operation by using the half-loop hysteresis of AFE. This work shows the feasibility of 3D vertical channel FeFETs and AFeFETs with OS channel for high-density storage memory.