[23a-B201-1~12] 10.4 Spintronics in semiconductor, topological material, superconductor, and multiferroics

[23a-B201-9] Evaluation of NiO barrier height in BiSb topological insulator/NiO/Co junctions

〇Shota Namba¹, Shigeki Takahashi², Yoshiyuki HIrayama², Pham Nam Hai¹ (1.Tokyo Tech, 2.Samsung R&D Inst. Japan)

Keywords:NiO, BiSb, SOT-MRAM

NiO interlayer is attracted attention in SOT-MRAM application. This can increase the spin injection efficiency by preventing interdiffusion and shunting with the spin current source. On the other hand, the NiO interlayer acts as a parasitic resistance, which reduces the TMR ratio and degrades the readout performance of SOT-MRAM.
In this study, we quantitatively evaluated the dependence of TMR ratio degradation on NiO film thickness by measuring the vertical resistance of BiSb/NiO/Co/Pt junctions deposited on sapphire substrates using four-terminal technique.