The 69th JSAP Spring Meeting 2022

Presentation information

Oral presentation

11 Superconductivity » 11.5 Junction and circuit fabrication process, digital applications

[23p-D214-1~19] 11.5 Junction and circuit fabrication process, digital applications

Wed. Mar 23, 2022 1:00 PM - 6:00 PM D214 (D214)

Shigeyuki Miyajima(NICT), Yuki Yamanashi(Yokohama Natl. Univ.)

5:00 PM - 5:15 PM

[23p-D214-16] Design of a Low-Area 4-bit Carry Lookahead Adder Using Clockless Logic Gates with Superconducting Single Flux Quantum Circuits

〇Taisei Fujisawa1, Yuki Yamanashi1, Nobuyuki Yoshikawa1 (1.Yokohama National Univ.)

Keywords:SFQ circuit, clockless logic gate, clockless XOR gate