[25p-E202-1~15] 21.1 合同セッションＫ 「ワイドギャップ酸化物半導体材料・デバイス」

▼ [25p-E202-5] Study of bottom-gate top-contact source-gated transistor for performance enhancement through device simulation

〇(D)Pongsakorn Sihapitak¹、Juan Paolo Soria Bermundo¹、Yukiharu Uraoka¹ (1.NAIST)

キーワード：amorphous InGaZnO, thin-film transistor, source-gate transistor

Thin-film transistor (TFT) is a fundamental element of display devices, which are the backbone technologies in our current world. As the technology of TFT is advanced, the problem of material quality is imminent and could decrease the performance of devices. To mitigate this problem that is common in TFTs is to combine oxide-semiconductor TFT with the Schottky diode. This new architecture which could provide stable output characteristics and is resilient to the material quality and process variation, is known as the Source-gate transistor or SGT. In order to design and optimize new structures and investigate their characteristics, ATLAS simulation [Silvaco] was used to simulate the reference TFT architecture. A reference amorphous InGaZnO (a-IGZO) TFT with a bottom-gate top-contact structure was fabricated. The fabricated device structure was recreated in ATLAS and the corresponding transfer and output characteristics were simulated. The density-of-state (DOS) of semiconductor material (IGZO) in the simulation is adjusted to approximate the experimental transfer characteristics. As the DOS has been tuned, the SGT device is simulated.